Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...

Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D ...

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

When semiconductor devices had geometries of 0.18 microns and larger, most defects manifested themselves as static faults. Test strategies based on stuck-at fault-model scan patterns and standard ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...