The 2006 International Test Conference is scheduled for the week of October 22 in Santa Clara, CA. For more on this year’s ITC, read our interview with program chair Anne Gattiker. Semiconductor test ...

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these ...

BALTIMORE — The marriage of design-for-test (DFT) software with test hardware may drastically lower the cost of test, according to several companies that will present their plans at this week's ...

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...

Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...

There's a growing demand for next-generation ICs to deliver the extreme performance required for fast-evolving applications, such as AI and self-driving cars, putting tremendous pressure on the size ...