IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Automatic PCB Material Characterization Using Design of Experiments and Mixed-Integer Sequential Quadratic Programming

Abstract: The growing demand for higher data rate SerDes channel calls for better PCB channel modelling. Conductor surface roughness can no longer be ignored, and it must be accurately modelled. PCB ...